부산대학교 도서관

This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time offset and the narrow range of the sampling phase detector (SPD), which would prevent fractional-N synthesis, a novel digital phase error correction (DPEC) technique, operating in the background, is introduced, which provides robust low-jitter performance. Besides, a novel frequency locking method is presented, which provides fast lock and seamless hand-off to main PLL operation. The PLL has been fabricated in a 28-nm CMOS technology process, and it synthesizes frequencies from 11.9 to 14.1 GHz, achieving an rms jitter of 58.2 and 51.7 fs (integrated into the 1 kHz–100 MHz bandwidth) for a fractional-N and integer-N channel, respectively. The reference spur is as low as −73.5 dBc, while the worst case near-integer fractional spurs are lower than −63.2 dBc. With a power consumption of 18 mW, the jitter-power figure of merit is −252.1 dB (fractional-N) and −253.3 dB (integer-N). The locking time is below 9 $\mu \text{s}$ for a 1-GHz frequency step. The synthesizer occupies 0.16 mm 2 , including decoupling capacitors.