부산대학교 도서관

Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high ${I}_{\text {on}}$ . One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable ${g}_{\text {m}}$ down to ${L}_{\text {g}} =25$ nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate ${g}_{m} =3.1$ mS/ $\mu \text{m}$ and ${R}_{\text {on}} = 190\,\,\Omega \mu \text{m}$ . This is the highest ${g}_{\text {m}}$ demonstrated on Si. Transmission line measurement verifies a low contact resistance with ${R}_{\text {C}} = 115\,\,\Omega \mu \text{m}$ , demonstrating that most of the MOSFET access resistance is located in the contact regions.