학술논문

Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
Document Type
Periodical
Source
IEEE Journal of the Electron Devices Society IEEE J. Electron Devices Soc. Electron Devices Society, IEEE Journal of the. 7:70-75 2019
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Logic gates
MOSFET
Scattering
Fabrication
Semiconductor device modeling
Resistance
Vertical
nanowire
InAs
InGaAs
heterostructure
Language
ISSN
2168-6734
Abstract
Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of $2.4 ~\text{mS}/\mu\text{m}$ , high on-current, and off-current below $1 ~\text{nA}/\mu\text{m}$ . An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance.