학술논문
A 33ns 64Mb DRAM
Document Type
Conference
Author
Source
1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International. :114-299 1991
Subject
Language
Abstract
This 3.3V 64Mb DRAM in a 176.4mm² die has 33ns typical RAS access time and 15ns typical column address access time. The key to small die and high reliability is an asymmetrical stacked trench capacitor (AST) cell in a pMOS centered inter-digitated twisted bit line (PCITBL) scheme. Three circuit techniques are developed to meet speed requirements: pre boosted wordline-driveline, bypassed sense-amplifier drive line and 3-stage differential amplifier with directly-driven data-out buffer.