학술논문
A sub-0.1 /spl mu/m circuit design with substrate-over-biasing [CMOS logic]
Document Type
Conference
Author
Source
1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) Solid-state circuits Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. :88-89 1998
Subject
Language
ISSN
0193-6530
Abstract
A substrate-over-biasing technique together with gate-substrate tie circuitry continues the downward trend of gate delay and reduces power for sub-0.1 /spl mu/m LSIs.