부산대학교 도서관

An 87.7 ${\hbox {mm}}^{2}$ 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques—octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme—reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of $\pm$220 mV is achieved even with the small cell size of 0.252 $ \mu{\hbox{m}}^{2}$. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.