학술논문

Hardware-Friendly Multiple Transform Selection Module for the VVC Standard
Document Type
Periodical
Source
IEEE Transactions on Consumer Electronics IEEE Trans. Consumer Electron. Consumer Electronics, IEEE Transactions on. 68(2):96-106 May, 2022
Subject
Power, Energy and Industry Applications
Components, Circuits, Devices and Systems
Fields, Waves and Electromagnetics
Transforms
Encoding
Standards
Complexity theory
Discrete cosine transforms
IEEE Sections
Software
Multiple transform selection
VVC
transform approximation
DCT
DST
complexity reduction
Language
ISSN
0098-3063
1558-4127
Abstract
The H.266/versatile video coding (VVC) standard is the most recent ITU/ISO video coding standard finalized in July 2020. VVC includes several new coding tools at different levels of the coding scheme. These coding tools enable a significant bitrate saving of up to 50% for the same subjective video quality than its predecessor H.265/high efficiency video coding (HEVC). Among these tools, we can cite the multiple transform selection (MTS) which selects at the encoder horizontal and vertical transforms among three trigonometrical transforms, including discrete cosine transform (DCT) type II, discrete sine transform (DST) type VII and DCT type VIII. Unlike the DCT-II, the DST-VII does not have efficient fast algorithmic implementation. Moreover, the MTS increases the memory usage required to store the coefficients of the three transforms. Consequently, this paper targets an efficient approximation of the DST-VII kernel based on the DCT-II and adjustment stage. The approximation of the DST-VII is modeled as an integer optimization problem jointly minimizing the error and the orthogonality of the approximate DST-VII under sparsity constraint of the adjustment stage. The sparse nonlinear optimizer (SNOPT) solver with an additional relaxation constraint is used to solve the problem and find the best sparse adjustment band matrices for different transform sizes. The DCT-VIII is then computed from the approximate DST-VII with pre/post processing operations involving only sign changes and input/output reordering. The proposed approximation provides a significant reduction in both arithmetic operations and memory usage. Moreover, it preserves the coding gain brought by the MTS under the VVC reference software. These advantages make our solution suitable for energy-efficient hardware H.266//VVC encoders and decoders deployed on consumer electronic devices.