학술논문
Lanthanum-Oxide-Doped Nitride Charge-Trap Layer for a TANOS Memory Device
Document Type
Periodical
Author
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 58(10):3314-3320 Oct, 2011
Subject
Language
ISSN
0018-9383
1557-9646
1557-9646
Abstract
A charge-trap-type Flash memory with a $\hbox{La}_{2}\hbox{O}_{3}$ -doped $\hbox{Si}_{3}\hbox{N}_{4}$ charge-trapping layer is demonstrated for the first time. An ultrathin $\hbox{La}_{2} \hbox{O}_{3}$ layer is inserted in the middle of a $\hbox{Si}_{3} \hbox{N}_{4}$ layer, followed by high-temperature annealing to mix the two layers. The $\hbox{La}_{2}\hbox{O}_{3}$-doped $\hbox{Si}_{3}\hbox{N}_{4}$ layer, irrespective of $ \hbox{Si}_{3}\hbox{N}_{4}$ deposition processes, is found to provide deep charge-trapping sites, resulting in an excellent pre-/postcycling retention property and high reliability. The optimization of the $\hbox{La}_{2}\hbox{O}_{3}$ layer thickness and position in the $\hbox{Si}_{3}\hbox{N}_{4}$ trapping layer has been also systematically studied.