부산대학교 도서관

An 8.8-mW, low-noise, 40.5-GHz frequency synthesizer is proposed. The synthesizer system consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a 900-MHz high-frequency-reference (HFR) PLL, and a novel subsampling lock detector (SSLD). The SSLD keeps monitoring the locking status of the SSPLL by sampling the SSPLL output with the HFR 900-MHz reference and automatically controls the SSPLL for frequency acquisition if it loses lock or locks to a wrong 100-MHz harmonic. This is done without using a power-consuming divider-based frequency-locked loop in conventional SSPLL. Due to the relatively low-frequency operation and moderate noise requirement of HFR, as well as the low-power SSLD, the proposed system achieves low power consumption and jitter simultaneously. The measured results show 8.8-mW power consumption and 228-fs rms jitter with in-band and out-band phase noises of −96.6 dBc/Hz at a 1-MHz offset and −106.9 dBc/Hz at a 10-MHz offset, respectively.