학술논문
A 40-Gb/s 14-mW CMOS Wireline Receiver
Document Type
Periodical
Author
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 52(9):2407-2421 Sep, 2017
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
A 40-Gb/s receiver includes a continuous-time linear equalizer, a discrete-time linear equalizer, a two-tap decision-feedback equalizer, a clock and data recovery circuit, and a one-to-four deserializer. Hardware minimization and charge steering techniques are extensively used to reduce the power consumption by a factor of ten. Fabricated in 45-nm CMOS technology, the receiver exhibits a bathtub curve opening of 0.28 UI with a recovered clock jitter of 0.5 ps rms .