학술논문
Junctionless nanowire transistor (JNT): Properties and design guidelines
Document Type
Conference
Author
Source
2010 Proceedings of the European Solid State Device Research Conference Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European. :357-360 Sep, 2010
Subject
Language
ISSN
1930-8876
2378-6558
2378-6558
Abstract
Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.