부산대학교 도서관

In VLSI domain there is an unending demand for low power, high speed and smaller chip area based circuits. Under these constraints, 1-bit magnitude comparator circuit (1B-MCC) is proposed using 12 Carbon Nanotube Field Effect Transistor (CNFET). However, the proposed analysis processes have been conducted in terms of power, delay and power-delay product (PDP). In order to arrive at a fair comparison between earlier designs and the proposed design, 2-bit magnitude comparator circuits (2B-MCC) are favored as they are designed in 45 nm CMOS technology at supply voltage (VDD) of 0.7 V. Later on the proposed design was extended to CNFET technology at 32 nm with VDD of 0.7 V to gain the benefits of CNFET technology.