학술논문
Design of a 60 GHz 32% PAE Class-AB PA with 2nd Harmonic Control in 45-nm PD-SOI CMOS
Document Type
Periodical
Author
Source
IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 67(8):2635-2646 Aug, 2020
Subject
Language
ISSN
1549-8328
1558-0806
1558-0806
Abstract
This paper presents a 60 GHz highly efficient singlestage differential stacked Class-AB power amplifier (PA) with second harmonic control (HC) for short range applications using mm-wave radar. The circuit is realized in a 45nm partially depleted sillicon-on-insulator (PD-SOI) CMOS technology. Measurement results show that the power amplifier achieves a saturated output power (P sat ) of 16.4dBm with a competitive maximum power-added efficiency (PAE max ) of 32% at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a single 1.8V supply and the chip core size is 0.36mm $\times\,\,0.35$ mm.