학술논문

45 nm Node Multi Level Interconnects with Porous SiOCH Dielectric k=2.5
Document Type
Conference
Source
2006 International Interconnect Technology Conference Interconnect Technology Conference, 2006 International. :213-215 2006
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Conductivity
Capacitance
CMOS technology
Delay
Copper
Electromigration
Atherosclerosis
Wire
Dielectric materials
Inorganic materials
Language
ISSN
2380-632X
2380-6338
Abstract
A 45nm node BEOL integration scheme is presented with 140nm metal pitch at local and intermediate levels and 70nm via size. The dual damascene (DD) process is performed in a full porous low-k (k=2.5) at line and via level in order to meet RC performance requirements. Parametrical results show functional via chains and good line resistance and serpentine continuity at 45nm node dimensions. Copper resistivity and electromigration performances were investigated for line widths below 50 nm upon using ALD and PVD barriers