부산대학교 도서관

The design phases of a sever product are often very long. It often takes average one and half years from feasibility study phase to mass production. The layout period is also usually at least one month due to larger board size and routing complexity. Although layout period is long, the arranged design review time is still limited. SI simulation and analysis method plays the important role in the design review phase.Channel Quality Check (CQC) is Intel channel analysis method with very high accuracy from PCB. CQC [1] [2] [3] is well-adopted by Intel customers during their high speed differential buses and memory channel designs. CQC can help system designers to check their channel designs are better or worse than a reference design or a specification from Intel. With just a few simulation cases in CQC methodology, OEM/ODM SI engineers can save tremendous simulation time in doing risk assessment of their designs but still keeping high simulation confidence level. However, CQC won’t give too much channel manufacture variation information.Units per Million (UPM) is also Intel channel analysis method. UPM first uses Design of Experiment (DOE) to scan manufacture variation and Response Surface Modeling (RSM) to form models of manufacture variation. UPM can be obtained by millions simulations using the models. UPM can provide vast information regarding all manufacture variations. The information may help engineers to make go/no go decision based on their own experience and engineering judgement. So some OEM/ODM SI engineers also use this method to do hundred to thousand SI simulations for their critical or challengeable products although it will spend much simulation time.However, comparing with PCB variables, the accuracy of variables of silicon and package designs are much less accurate due to extremely complicated silicon design. Therefore PCB board designers prefer to focus on the analysis of PCB variables rather than considering inaccurate silicon variables as well if possible.