학술논문
Implant dose sensitivity of 0.1 /spl mu/m CMOS inverter delay
Document Type
Conference
Author
Source
Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design Asia-South Pacific design automation and VLSI design Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.. :225-230 2002
Subject
Language
Abstract
The simulation experiment is performed to characterize the impact of process level fluctuations on the circuit performance variation for the 0.1 /spl mu/m CMOS technology. The 0.1 /spl mu/m NMOS and PMOS transistors are optimized using four different ion implantation steps namely super steep retrograde channel (SSRC) implant, deep s/d implant, shallow s/d extension implant and halo implant. We demonstrate that the fluctuations in the nominal values of these implant doses result in the significant variation in DC (I/sub off/, I/sub on/, V/sub t/) and AC (C/sub gg/) parameters of the transistors. The DC and AC parameter variations of these devices in turn have their effect on the performance of the inverter circuit. In particular, the halo implant has the maximum impact resulting in /spl Delta/I/sub off/=122% (97.48%) and /spl Delta/I/sub on/=4.82% (5.29%) for NMOS (PMOS) transistor. The worst case delay variation is more than /spl plusmn/10% for a /spl plusmn/10% random variation in the implant dose parameters.