학술논문

High speed FPGA implementation of hough transform for real-time applications
Document Type
Conference
Source
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on. :213-218 Apr, 2012
Subject
Components, Circuits, Devices and Systems
Random access memory
Field programmable gate arrays
Pipeline processing
Memory management
Equations
Pipelines
Language
Abstract
Hough Transform (HT) is a popular line detection algorithm in image processing and machine vision applications, favored for its tolerance to noise and partial occlusion. However, due to its computational complexity, software and hardware implementations for real-time video processing are usually limited to low resolutions and frame rates. We propose a novel architecture that exploits modern FPGA inherent parallelism capabilities, combined with efficient resource utilization and deep pipelining to enable real-time processing of high resolution, high frame rate videos.