학술논문
Design of configurable power efficient 2-dimensional crossbar switch for network-on-chip(NoC)
Document Type
Conference
Author
Source
2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Recent Trends in Electronics, Information & Communication Technology (RTEICT), IEEE International Conference on. :1514-1517 May, 2016
Subject
Language
Abstract
Network-on-Chip is an emerging paradigm for integrating very high number of Intellectual Property blocks on a single Integrated Chip. In this paper, crossbar switch is designed for 2-D Mesh Network-on-Chip to meet the current requirements of high speed networks. The design reduced the power consumption significantly and can meet the scalable bandwidth. The functional verification of the crossbar switch design using ModelSim 6.4a has been shown. Synthesis has been performed on Xilinx 13.3 and it is verified using FPGA.