학술논문
A Novel Approach to Design SAR-ADC: Design Partitioning Method
Document Type
Periodical
Author
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 35(3):346-356 Mar, 2016
Subject
Language
ISSN
0278-0070
1937-4151
1937-4151
Abstract
This paper presents a successive approximation register analog-to-digital converter (SAR-ADC) design optimization platform. A novel ADC modeling approach, design partitioning method (DPM), is used in the proposed platform. It uses lookup tables along with conventional behavioral modeling technique, which captures the design parameters and process nonidealities. An individualistic as well as collective study of the impact of these parameters and nonidealities on the performance of SAR-ADC has been carried out. The proposed platform aims to achieve a perfect balance between architecture evaluation time (3.2% with respect to SPICE netlist) and accuracy in performance estimation (98% with respect to SPICE netlist). A comparative study between SPICE model, structural modeling, and the proposed modeling scheme (DPM) is reported here. As a case study, a 14-bit, 4.2MSPS SAR-ADC architecture is evaluated, designed, and verified.