학술논문
Design and development paradigm for industrial formal verification CAD tools
Document Type
Periodical
Source
IEEE Design & Test of Computers IEEE Des. Test. Comput. Design & Test of Computers, IEEE. 18(4):26-35 Aug, 2001
Subject
Language
ISSN
0740-7475
1558-1918
1558-1918
Abstract
CAD tool designers have given priority to providing features that will let circuit and logic designers use this custom-memory formal verification and analysis tool without a steep learning curve. This article discusses a few fundamental design decisions behind the successful deployment of a second-generation formal custom-memory equivalence-checking tool, Versys2, in the PowerPC design flows. The Versys2 symbolic simulator was developed at Motorola for verifying equivalence between register-transfer-level (RTL) designs and custom transistor circuit schematics.