학술논문
Physical Understanding of SANOS Disturbs and VARIOT Engineered Barrier as a Solution
Document Type
Conference
Author
Source
2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE. :94-95 Aug, 2007
Subject
Language
ISSN
2159-483X
2159-4864
2159-4864
Abstract
Both read and program disturb sensitivity are identified to be major drawbacks for nitride-based NAND Flash arrays. The crucial aspects to understand the disturbs are the injection of electrons at low fields through the bottom oxide, and the tunneling through the top oxide during programming. These results are exploited to identify possible improvements of the device. A VARIOT engineered barrier is proposed to replace the bottom oxide layer in order to significantly reduce the disturb problem.