학술논문
A post-silicon clock timing adjustment using genetic algorithms
Document Type
Conference
Author
Source
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) VLSI circuits VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on. :13-16 2003
Subject
Language
Abstract
A post-silicon clock timing adjustment architecture utilizing genetic algorithms (GA) is proposed, which has three advantages: (1) enhanced clock frequency leading to improved operating yields, (2) lower power supply voltages while maintaining operating yield, and (3) reductions in design times. Experiments with two different developed LSI chips and a design experiment demonstrated these advantages with a clock frequency enhancement of 25% (max), a power supply voltage reduction of 33%, and 21% shorter design times.