학술논문
An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions
Document Type
Conference
Author
Source
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Custom integrated circuits conference Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002. :345-348 2002
Subject
Language
Abstract
We have developed an LSI for Gm-C IF filters, attaining (1) a 63% reduction in filter area, (2) a 38% reduction in power dissipation, compared to existing commercial products, and (3) a yield rate of 97%. The developed chip is calibrated within a few seconds by a genetic algorithm; an efficient AI technique for difficult optimization problems.