학술논문
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods
Document Type
Periodical
Author
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 27(12):2223-2235 Dec, 2008
Subject
Language
ISSN
0278-0070
1937-4151
1937-4151
Abstract
This paper presents two symbolic model checking algorithms for the verification of analog/mixed-signal circuits. The first model checker utilizes binary decision diagrams while the second is a bounded model checker that uses a satisfiability modulo theory solver. Both methods have been implemented, and preliminary results are promising.