부산대학교 도서관

Conventional designs of the extensively studied resistive-random access-memory (RRAM) cell involve one transistor and one RRAM—“1T1R,” i.e., two separate devices thereby constraining its integration density. In this work, we overcome this longstanding limitation by experimentally demonstrating a novel memory architecture that combines the 1T and 1R into a single hybrid device by uniquely leveraging both lateral and vertical van der Waals (vdW) heterostructures. This ultracompact device, which can be considered as a “0.5T0.5R” memory cell, reduces the device count by half—the first of its kind in RRAM technology history, and simultaneously allows higher lateral as well as vertical (3-D) integration density w.r.t. the conventional 1T1R architecture. The unique “smart” device that can retain information after power is turned off is structurally designed by utilizing a shared graphene edge-contact and resistively switchable hexagonal boron nitride ( ${h}$ -BN) insulator. Aided by design optimization, record performance (1000), benchmarked against current vdW-material-based RRAM devices, have been achieved by this 0.5T0.5R memory cell. Moreover, the RRAM’s fine tunability with ultrashort pulsewidth, pulse amplitude, and gate voltage, enables synaptic plasticity and makes it an integrated three-terminal RRAM with considerable potential for neuromorphic and in-memory computing applications.