학술논문
CMOS implementation of a 32 b computer
Document Type
Conference
Author
Allmon, R.L.; Bowhill, W.J.; Benschneider, B.J.; Brown, J.F.; Cooper, E.M.; Durdan, W.H.; Fisher, A.; Gavrielov, M.N.; Gronowski, P.E.; Grundmann, W.J.; Herrick, W.V.; Kravitz, D.; Madden, L.C.; Maheshwari, V.K.; Marcello, R.C.; Mills, G.G.; Mittal, M.; Peng, V.; Pickholtz, J.D.; Samudrala, S.; Sanders, D.E.; Stamm, R.L.; Starvaski, P.J.; Wheeler, W.R.
Source
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International. :80-81 1989
Subject
Language
Abstract
A four-chip custom VLSI implementation of a 32-b computer comprised of a CPU, a secondary cache controller, a floating-point accelerator, and a clock generator is described. It operates at a cycle time of 28 ns and is compatible with an existing computer architecture. The chip set is fabricated in a 1.5- mu m n-well, double-layer-metal CMOS process and includes over 650000 transistors. The CPU is a six-level pipeline engine built around three semiautonomous pipes. These provide simultaneous instruction prefetch and decode, specifier decode and execution, memory management, and I/O access. The CPU averages nine cycles/instruction on typical benchmarks. Chip functionality is verified through test vectors at the pins, with stuck-at fault coverage greater than 95%, and complete control store and cache tests. Summaries of process characteristics and physical specifications are presented.ETX