부산대학교 도서관

The development of a fully synthesizable 32-bit processor using the open-source and free RISC-V (RV32I) ISA is described in this work. Low Cost embedded devices were considered when designing this CPU. The framework for RISC-V development and validation, which includes putting together tools and automated test suites, is also provided in this document. The final processor will be a RISC-V processor with a single core and simple hardware. Verilog HDL is used to develop the recommended CPU, and a "Artix-7" FPGA board is used to further prototype it. This shows that the maximum operational frequency is 32MHz. With an initial focus on FPGA design and then SoC design later on, this article describes the design chores from high architectural level descriptions down to RTL and then proceeding through logic synthesis and physical design to get the layout ready for its final tapeout in CMOS 90 nm technology.