학술논문

A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving −96.4-dBm Sensitivity and −27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets
Document Type
Periodical
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 55(12):3376-3386 Dec, 2020
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Receivers
Attenuators
Transceivers
Gain
Transistors
System-on-chip
Radio frequency
All-digital phase-locked loop (ADPLL)
blocker-resilient receiver
Bluetooth low energy (BLE)
low-noise transconductance amplifier (LNTA)
time-to-digital converter (TDC)
transceiver
ultra-low-power radio
Language
ISSN
0018-9200
1558-173X
Abstract
This article presents a 0.5-V RF transceiver fully compliant with Bluetooth low energy (BLE) standards. The receiver (RX) fabricated in a 22-nm fully depleted silicon on insulator (FD-SOI) process achieves a sensitivity of −96.4 dBm, an intermodulation tolerance of −27 dBm for interferers at 6- and 12-MHz offsets, while consuming 1.9 mW. An RX-chain with a gain-programmable low-noise transconductance amplifier (LNTA) provides good linearity over a wide input power range. The LNTA changes amplifier topology according to the gain setting. It achieves a gain range of 41 dB and the IIP3 of −13 dBm at maximum gain. The proposed asynchronous SAR-ADC-based time-to-digital converter (TDC) for the all-digital phase-locked loop (ADPLL) is suitable for low-voltage operation and low-power consumption. It achieves a differential nonlinearity (DNL) of ±0.62 LSB and an integral nonlinearity (INL) of ±0.63 LSB.