학술논문
Fin Bending Mitigation and Local Layout Effect Alleviation in Advanced FinFET Technology through Material Engineering and Metrology Optimization
Document Type
Conference
Author
Wen, T.Y.; Colombeau, B.; Li, C.l.; Liu, S.Y.; Guo, B.N.; Meer, H.V.; Hou, M.; Yang, B.; Feng, H.C.; Hsu, C.F.; Huang, C.C.; Tasi, Y.T.; Chen, H.P.; Huang, S.A.; Huang, C.W.; Chen, C.H.; Lin, J.C.; Shim, K.H.; Kuo, J.; Lee, S.; Holcman, L.; Nafisr, K.; Fernandez, J.; Fung, D.; Yang, N.H.; Wu, J.Y.; Hung, G.C.
Source
2019 Symposium on VLSI Technology VLSI Technology, 2019 Symposium on. :T110-T111 Jun, 2019
Subject
Language
ISSN
2158-9682
Abstract
In advanced FinFET devices, STI gap fill and $\vert \text{LD}_{0}$ stress are responsible for fin defects, fin bending as well as device performance degradations due to the local layout effect (LLE). In this paper, for the first time, we look at different ways to modulate the stress from the Flowable CVD (FCVD) films either by additional UV treatment and/or ion beam treatment (hot Helium implantation). By leveraging in-line e-beam metrology capabilities of PROVision™ for massive measurements of critical dimensions (CDs), the process impact on fin spacing and LLEs are characterized and analyzed. Significant improvement for LLE is observed for nFET device which correlates to fin bending improvement. In addition, ~5% drive current gain for pFET is observed after $\text{ILD}_{0}$ stress optimization.