부산대학교 도서관

As data sizes increase exponentially, the demand for higher-density NAND with a smaller cell size and a higher interface speed has also increased [1]–[4]. However, the increased number of WL-stack layers results in a smaller sensing circuit size and a smaller WL-to-WL spacing, which increases the intrinsic transistor variation and the inter-cell interference. One way to achieve good density while maintaining system performance is to support more multiple-plane operations with a circuit under cell array architecture, which leads to an increased noise power. Moreover, to achieve a 2.4Gb/s the I/O circuits need to support the faster speed while achieving lower power consumption. This paper presents the offset cancelling sensing latch (OCSL) scheme, the quad-group interference-free read (Q-IFR) scheme, and the common-source line (CSL) noise-tracking scheme to resolve the aforementioned challenges. In terms of the high-speed I/O bandwidth, a receiver circuit and an internal reference voltage generator are also proposed to increase the I/O speed, reduce the standby power consumption, and reduce the settling time when the chip is enabled.