학술논문

Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits
Document Type
Conference
Source
2017 47th European Solid-State Device Research Conference (ESSDERC) Solid-State Device Research Conference (ESSDERC), 2017 47th European. :192-195 Sep, 2017
Subject
Bioengineering
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Aging
Integrated circuit modeling
Stress
Mathematical model
MOSFET
Semiconductor device modeling
Threshold voltage
aging simulation
carrier traps
dynamic change
self-consistent solution
Language
ISSN
2378-6558
Abstract
A compact aging model for circuit simulation has been developed by considering all possible trapped carriers within MOSFETs. The hot carrier effect and the N(P)BTI effect are modeled by integrating the substrate current as well as the oxide field change due to the trapped carriers. Additionally, the carriers trapped within the highly resistive drift region are included for high-voltage (HV)-MOSFET modeling. The aging model considers the dynamic trap-density increase as a function of circuit-operation time with dynamically varying stress conditions for each individual MOSFET. A self-consistent solution is obtained by iteratively solving the Poisson equation including the trap density. The model is verified to be applicable for any type of MOSFETs covering advanced technologies as well as HV-MOSFETs.