부산대학교 도서관

Nowadays, use of higher carrier frequencies for data transmission in wireless communication has created a demand for Direct RF Sampling ADCs with higher sampling clocks and larger analog bandwidths. With the increase in the data rate of ADCs there is a need for the higher clock speed capable ASIC/FPGAs for faster acquisition and efficient signal processing. Though ASICs are the best method to achieve required clock speeds for faster acquisition their NRE Costs, Fabrication cost and Time to market put them in the second position when compared to FPGAs which are highly reconfigurable, features less time to market and cost effective. While today the maximum clock speeds which the popular FPGAs could achieve are around 500MHz, the sampling clock requirements of typical high speed ADCs are much higher and range from 200MHz to 3GHz. Hence in order to facilitate for such high data throughput handling, ADCs typically provide data in DDR and polyphase fashion which can be acquired at lower clock speeds by FPGA. This paper presents such an interface where a bandpass data on S-band @ 2.9GHz is directly sampled by a 12-bit ADC and 1 GSPS sampled data is interfaced with Xilinx Virtex-5 FPGA with an operating clock of 250MHz through DDR dual port. It is further downconverted using a polyphase mixer to process signal chains directly without use of DCMs and FIFOs. It is further fed to a polyphase FIR Decimation filter of order N = 320 for efficient baseband translation. Two stage optimization is proposed for reducing hardware complexity of filter. Firstly, coefficient symmetry is exploited and the number of polyphase paths are reduced by half. Secondly, coefficient multipliers are resued to further reduce the hardware resources. The design is a complete custom design without use of IP Cores to make it independent of FPGA/ASIC flow. The algorithm is implemented in Xilinx virtex-5 FPGA and tested on a custom board mounted with ADC and FPGA.