부산대학교 도서관

Using a full device-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner $\left(\mathrm{L}_{\mathrm{G}(\mathrm{I})}\right)$- and outer $\left(\mathrm{L}_{\mathrm{G}(\mathrm{O})}\right)$- gates in gate-all-around nanosheet FETs. A better trade-off between short-channel effects ($\mathrm{S}_{S A T}$), external resistance $\left(\mathrm{R}_{\mathrm{EXT}}\right)$, effective favors for a more aggressive $\mathrm{L}_{G(O)}$ scaling (reduces C CARA and/or relaxes contact length, $\mathrm{L}_{\mathrm{CNT}}$) keeping $\mathrm{L}_{\mathrm{G}(\mathrm{I})}$ relaxed (controls $\mathrm{R}_{\mathrm{EFF}}, \mathrm{S}_{\mathrm{SAT}}$). Up to 10% speed-at-iso-leakage, 11% speed-at-iso-power, and 15% power-at-iso-speed gains are possible with this design, in addition to allowing better contact-poly pitch (CPP) scaling path.