학술논문

A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC
Document Type
Conference
Source
2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) Circuits & Systems (LASCAS), 2016 IEEE 7th Latin American Symposium on. :315-318 Feb, 2016
Subject
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Photonics and Electrooptics
Microcontrollers
Protocols
Bridge circuits
Registers
Random access memory
Computer architecture
Integrated circuit interconnections
Language
Abstract
In this paper a complete implementation and design of a fully-synthesized 32-bit microcontroller in a 130nm CMOS technology is presented. This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process. The microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an 8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for output verification, and an SPI APB slave interface for checking the correct behavioral of the APB bridge. All peripherals are controlled by a RISC-V and an SPI AXI master interface that is used for programming the device and checking the data flowing through all the slaves. A total power density is reported as 167μW/MHz and the area for this RISC-V microcontroller has a reduced footprint of 798μm×484μm.