부산대학교 도서관

A low dropout regulator (LDO) is designed in 55nm CMOS technology. It is targeted for high-end audio applications, which present continuous-time as well as switched-capacitor building blocks. A multiple loop capacitor-less structure is proposed to cope with both high power supply rejection ratio (PSRR) and fast transient response. In particular, a folded flipped voltage follower (FFVF) output buffer presents a fast inner loop, needed to detach the error amplifier (EA) from the load capacitor $(C_{L})$ and drive this latter under fast transients. A variable resistance and adaptive biasing are developed to guarantee stability under all load conditions, including $I_{L}=0$. Moreover, a slower high-gain loop is designed to set the output potential $V_{out}$, further reducing the output impedance and improving the PSRR, line and load regulation. The proposed LDO is implemented using IO high threshold transistors and provides an output voltage $V_{out}=1\ \mathrm{V}$ from a $1.2 \mathrm{V}\pm 10\%$ supply with a minimum possible dropout $(V_{drop}^{min})$ of 80 mV. It achieves a worst-case low-frequency PSRR of −76.2 dB under Montecarlo simulations (MC) and a recovery time of 142 ns when a load spike of $800\ \mu \mathrm{A}$ is applied. Line and load regulation are 0.001 mV/V and 0.007 mV/mA. Moreover, the quiescent current $(I_{q})$ is less than $20\ \mu \mathrm{A}$ at maximum $I_{L}$.