학술논문
Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic
Document Type
Conference
Author
Source
2015 Symposium on VLSI Technology (VLSI Technology) VLSI Technology (VLSI Technology), 2015 Symposium on. :T206-T207 Jun, 2015
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary ‘all III–V’ Heterojunction Vertical Tunnel FET (HVTFET) with record performance at |V DS |=0.5V. The p-type TFET (PTFET) has I ON =30µA/µm and I ON /I OFF =10 5 , whereas the n-type TFET (NTFET) has I ON =275µA/µm and I ON /I OFF =3×10 5 , respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low V DD logic applications.