학술논문
Identifying Reliability High-Correlated Gates of Logic Circuits With Pearson Correlation Coefficient
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 71(4):2319-2323 Apr, 2024
Subject
Language
ISSN
1549-7747
1558-3791
1558-3791
Abstract
Identifying reliability high-correlated gates (HRCGs) is vital for fault location and exclusion, especially for cascading faults. By executing a linear fit based on the results of the circuit’s reliability evaluation and calibrating the fit function using regression residual analysis, this brief first proves the existence of HRCGs. A time-series-oriented PCC model is then introduced to quantify gates’ reliability correlation (GRC) and identify all the HRCGs in the circuit. Circuit-correlated primary outputs and sequential circuit-correlated flip-flops were further identified based on this approach. Experimental results on benchmark circuits show that the average accuracy of this approach is 0.9972 with the Monte Carlo (MC) method, and it is 2591 times faster than the MC method. On larger circuits, the identification rate and stability are 6.07 times and 13.55 times greater than the reference method and rand method, respectively.