부산대학교 도서관

In the post-Moore era, chiplet heterogeneous integration technology is gaining attention as a way to address the scaling limitations of monolithic chips. The Universal Chiplet Interconnect Express (UCIe) standard defines a complete stack for inter-chiplet communication, ensuring interoperability among chiplets. This paper introduces MUG5, a UCIe link model that enables accurate latency estimation through gem5-based simulation. The targeted mode of operation in UCIe is PCIe 6.0 with standard 256B flit (flow control unit). The model focuses on flit packing and Ack/Nak-based retry mechanism. We validate the model on two commonly used system topologies, and the results demonstrated that its deviation is within 0.04ns.