학술논문
A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing
Document Type
Conference
Author
Source
International Electron Devices Meeting. IEDM Technical Digest Electron Devices Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International. :851-854 1997
Subject
Language
ISSN
0163-1918
Abstract
A 0.25 /spl mu/m CMOS technology, with 6 layers of fully planarized interconnect, has been developed for versatile, flexible, and fast turn-around foundry manufacturing. A 0.6 /spl mu/m layout pitch has been successfully demonstrated for active, gate poly, and first metal layers. The 0.25 /spl mu/m, 50 A Tox and the 0.35 /spl mu/m, 65 A Tox devices were designed to support the 2.5 V core and the 3.3 V I/O circuits respectively on the same chip. In addition, high-performance 0.18 /spl mu/m, 40 A Tox transistors are also available for low-power applications at 1.8 V Vcc. Gate-delay is 40 p-sec at 2.5 V for the 0.25 /spl mu/m device, and 35 p-sec at 1.8 V for the 0.18 /spl mu/m device. The embedded 6 T SRAM cell size is 6.34 /spl mu/m/sup 2/. Considerations in process architecture and device design, relevant to foundry manufacturing, are also addressed on this 6-level-metal 0.25 /spl mu/m CMOS technology.