학술논문
Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation
Document Type
Conference
Author
Source
2024 International Conference on Electronics, Information, and Communication (ICEIC) Electronics, Information, and Communication (ICEIC), 2024 International Conference on. :1-3 Jan, 2024
Subject
Language
ISSN
2767-7699
Abstract
This paper proposes a clock buffer with compensator technology to achieve low-jitter design in the digitally controlled oscillator (DCO). The compensator consists of a PMOS transistor and a MOS capacitor. The compensator that provides the opposite sensitivity to the delay cell is connected to the node between each delay cell. The compensated DCO has a reduced jitter of approximately 12.7-ps (peak-to-peak) based on the 3-GHz output frequency under ±0.1% VDD noise.