학술논문
Self-Aligned in 2Pitch Cell Array Transistor (S2CAT) for 4F2 Based DRAM Generation Extension
Document Type
Conference
Author
Park, Seokhan; Oh, Gyuhwan; Yoo, Bowon; Jeong, Moonyoung; Lee, Kiseok; Lee, Sangho; Hong, Seongbin; Sung, Sang Hyun; Choi, Hyungeun; Jo, Taegeun; Jang, Wonchul; Park, Jaekyun; Park, Sangwuk; Yun, Hyunchul; Kim, Jinbum; Jang, Sunghwan; Kuh, Bong-Jin; Kim, Ilgweon; Oh, Jeonghoon; Han, Jin-Woo; Park, Jemin
Source
2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023
Subject
Language
ISSN
2156-017X
Abstract
This paper presents a novel 4F 2 DRAM cell transistor for future DRAM. Whereas traditional 4F 2 vertical channel transistor (VCT) were based on gate-all-around (GAA) structure, the self-aligned in 2-pitch cell array transistor (S2CAT) in this work uses a back-gate (BG) shared by two neighboring bit cells. A voltage biased to BG controls threshold voltage (V T ), which is used to suppress the leakage current. In order to mitigate the process induced bending and leaning of the thin and tall Si structure and improves channel thickness uniformity, the spacer of BG mask is used to self-align pattern two Si vertical channels. A proposed concept is verified by fabrication and measured switching characteristics.