학술논문
A novel integration of STT-MRAM for on-chip hybrid memory by utilizing non-volatility modulation
Document Type
Conference
Author
Park, J.-H.; Lee, J.; Jeong, J.; Pi, U.; Kim, W.K.; Lee, S.; Noh, E.; Kim, K.; Lim, W. C.; Kwon, S.; Bae, B.-J.; Kim, I.; Ji, N.; Lee, K.; Shin, H.; Han, S. H.; Hwang, S.; Jeong, D.; Oh, S. C.; Park, S. O.; Song, Y. J.; Jeong, G. T.; Koh, G. H.; Hyun, S.; Hwang, K.; Nam, S. W.; Kang, H. K.; Jung, E. S.
Source
2019 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2019 IEEE International. :2.5.1-2.5.4 Dec, 2019
Subject
Language
ISSN
2156-017X
Abstract
We demonstrate a novel way of integrating STT-MRAM for on-chip hybrid memory which exhibits either features of high-retention or high-speed implemented in separate zones in a single chip. For satisfying high-temperature retention requirement, tailored MTJs are shown to support > 10 year retention at 220°C. For high-speed operation, critical improvements have been made in terms of TMR, short fail probability, overdrive and write error rate. The new integration provides a manufacturable way of combining diverse memory components by modulating non-volatility of STT-MRAM without affecting within-chip distributions of critical properties.