학술논문
A 1-1.7 GHz Cryogenic Fractional-N CP-PLL for Quantum Computing Applications
Document Type
Conference
Author
Source
2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2023 IEEE 66th International Midwest Symposium on. :172-176 Aug, 2023
Subject
Language
ISSN
1558-3899
Abstract
In this paper, we derive the difference of phase-lock-loop(PLL) parameters under cryogenic temperature and room temperature according to the characterization of MOSFET under 3.5K. Then, we discuss the noise source under cryogenic temperature and optimize PLL design based on the discussion above. Finally, a 1 to 1.7 GHz fractional-N CP-PLL working under 3.5K is proposed to validate our design methodology. The proposed PLL has been fabricated in 28-nm bulk CMOS process. At 3.5K temperature, the PLL achieves phase noise of - 122.7dBc/Hz @ 1MHz and 2.2ps fractional-N RMS jitter, which are ~10dB and 3.4ps lower than that under room temperature. With a supply voltage of 0.9V, the power consumption is 1.52mW under cryogenic temperature, which is 0.5mW lower than that under room temperature.