부산대학교 도서관

Development of advanced logic design nodes requires accelerated identification of yield limiting defect types. Missing vias in back end of line (BEOL) is a key defect of interest driving the need for a reliable process control method to monitor the defect inline, prior to final test. In this paper we introduce a novel inspection strategy called nano·cell™, which is integrated on advanced broadband plasma patterned wafer defect inspection tools. Nano·cell™ inspection methodology enables the definition of 2-dimensional mask-based design care areas in repeating patterns of interest. When applied to via chain structures, this method enabled unique capture of the missing via defect type over existing detection methods. In addition to sensitivity improvement, this technique reveals and characterizes systematic defectivity within repeating array cells that correlates to wafer-level signatures, demonstrating new insights to be gained with cell-level defectivity characterization.