학술논문
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
Document Type
Periodical
Author
Bulzacchelli, J. F.; Menolfi, C.; Beukema, T. J.; Storaska, D. W.; Hertle, J.; Hanson, D. R.; Hsieh, P.-H.; Rylov, S. V.; Furrer, D.; Gardellini, D.; Prati, A.; Morf, T.; Sharma, V.; Kelkar, R.; Ainspan, H. A.; Kelly, W. R.; Chieco, L. R.; Ritter, G. A.; Sorice, J. A.; Garlett, J. D.; Callan, R.; Brandli, M.; Buchmann, P.; Kossel, M.; Toifl, T.; Friedman, D. J.
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 47(12):3232-3248 Dec, 2012
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28 $~$Gb/s is 693 mW/lane.