학술논문
An 0.8 µm CMOS technology for high performance logic applications
Document Type
Conference
Author
Source
1987 International Electron Devices Meeting IEDM Tech. Dig. Electron Devices Meeting, 1987 International. :362-365 1987
Subject
Language
Abstract
This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.