부산대학교 도서관

Synchronous Dynamic Random Access Memory (SDRAM) can transmit data much quicker than asynchronous RAM. It is very important for data flow; a memory controller with high speed is required. High-performance digital circuits may be designed using an optimization approach called parallel pipeline register architecture. This work proposes a novel pipeline register design for high-speed communication. The structure consists of many stages, each responsible for executing a unique function in concert with the others. The data is saved in the pipeline register while it is being processed in the different phases of the pipeline. The user module and the memory controllers communicate with each other by a rapid memory link connection and data connection. Results show that the FPGA design of the proposed design is possible, and the Xilinx 13.1 ISE simulator's performance show that the proposed design improves the performance of digital circuits with less latency and high throughput.