학술논문
ESD protection design for high-speed applications in CMOS technology
Document Type
Conference
Author
Source
2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2016 IEEE 59th International Midwest Symposium on. :1-4 Oct, 2016
Subject
Language
ISSN
1558-3899
Abstract
To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded silicon-controlled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.