학술논문
High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond
Document Type
Conference
Author
Oh, H.J.; Kim, J.Y.; Kim, J.H.; Park, S.G.; Kim, D.H.; Kim, S.E.; Woo, D.S.; Lee, Y.S.; Ha, G.W.; Park, J.M.; Kang, N.J.; Kim, H.J.; Hwang, J.S.; Kim, B.Y.; Kim, D.I.; Cho, Y.S.; Choi, J.K.; Lee, B.H.; Kim, S.B.; Cho, M.H.; Kim, Y.I.; Choi, J.; Shin, D.W.; Shim, M.S.; Choi, W.T.; Lee, G.P.; Park, Y.J.; Lee, W.S.; Ryu, B.I.
Source
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Solid-State Device Research Conference Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European. :177-180 2005
Subject
Language
ISSN
1930-8876
2378-6558
2378-6558
Abstract
For the first time, the DRAM device composed of 6F/sup 2/ open-bit-line memory cell with 80nm feature size is developed. Adopting 6F/sup 2/ scheme instead of customary 8F/sup 2/ scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F/sup 2/ accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F/sup 2/, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V/sub th/ so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (sphere-shaped-recess-channel-array transistor) is introduced. It is the improved scheme of RCAT used in 8F/sup 2/ scheme. By adopting S-RCAT, V/sub th/ can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.