학술논문

A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications
Document Type
Periodical
Author
Source
IEEE Solid-State Circuits Letters IEEE Solid-State Circuits Lett. Solid-State Circuits Letters, IEEE. 7:127-130 2024
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Single-photon avalanche diodes
Histograms
Laser radar
Photonics
Time-frequency analysis
Linearity
Shape
Dual gated-ring oscillator (dual GRO)
extended counting
incremental TDC
mean detection method
phase-domain delta–sigma (PDΔΣ) TDC
single-photon avalanche diode (SPAD)
time-to-digital converter (TDC)
Language
ISSN
2573-9603
Abstract
This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD $\Delta \Sigma$ ) TDC. The proposed TDC operates in an incremental $\Delta \Sigma $ manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of $2000~\mu \text{m}~^{\mathrm{ 2}}$ . It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.